#define LFDS611_BARRIER_PROCESSOR_READ [compiler read processor barrier directive]
No return value.
Processors typically are able to re-order the flow of instructions, where this re-ordering is only guaranteed to be valid within the context of a single thread; e.g. if thread A performs an operation and then raises a flag, where thread B is waiting on the flag, the processor will in its re-ordering only take into account that the behaviour of the thread being re-ordered remains valid, such that in this case we might see in thread A the flag being raised before the operation is performed, since the processor isn't taking into account that thread B is written on the assumption the flag will be raised after the operation.
Compilers typically offer a directive which acts as a red processor barrier, where a red processor barrier the prevents the processor re-ordering load operations below the barrier above the barrier and prevents the processor re-ordering load operations above the barrier to below the barrier.
Under MSVC, there is a compiler intrinsic _mm_lfence(), which has the following prototype;
As such, the implementation of LFDS611_BARRIER_PROCESSOR_READ on MSVC looks like this;
#define LFDS611_BARRIER_PROCESSOR_READ _mm_lfence()
Note there is no trailing semi-colon. It is however harmless to have it in the #define.