I’m going to go back to run-time alignment.
I think when I first did this ages ago I failed to realise that the ERG size would always be a positive integer mutiple of the cache-line size, and so I thought there had to be some math done to figure out the correct atomic isolation size.
Run-time alignment is necessary because of ARM.
Where the ERG size is 8 to 2048 bytes, and the code fails completely if the ERG is set too small, you basically have a problem and/or need to be pessimistic, and it’s painful to set a large ERG.
I also need people to be *aware* of the whole ERG issue, and I really don’t want that. I want them to be able to pick up the data structures like they’re normal and just use them.
Run-time isn’t needed on Intel, which has fixed cache line sizes – although, ha – I’m already treating them as a pessimistic case, since Intel these days usually transfers two cache lines at a time, something you can turn off in the BIOS on some machines.