So, I’ve been sorting out usiing the stack for allocations, e.g. providing #defines with the necessary data for array sizes.
I’ve also been fixing up the run-time cache-line alignment #defines, sorting them out after recent widespread changes (from all the SMR work) to state structures.
What I realised was that where any load or store inside an ERG (the ARM exclusive reservation granuale, the zone in which a given LL/SC pair is sensitive to other bus activity) breaks the LL/SC, the critical pointers in DSIs need to have their own ERG page. But they also need to be cache line aligned! and you can only work out the least common multiple of two numbers iteratively – there’s no closed solution, so you can’t create a #define.
This is okay for freelist and stack, because there’s only one critical pointer – so I just pad that to the larger of cache line with / ERG size, and then the following state members coould on ARM be non-cache line aligned, but that’s okay.
But it’s a problem for the queue state, because that has *two* critical pointers, enqueue and dequeue. So the padding between enqueue and dequeue MUST place dequeue on an ERG boundary and be cache line aligned – which you cannot work out in a #define… which seemed to sink run-time alignment!
HOWEVER, I’ve just reaised – I think on ARM the memory you work with does not have to be cache line aligned! ARM doesn’t use MESI to implement CAS, so it isn’t necessary. So I don’t need to work out the least common multiple – all I need to do is on ARM for padding, use ERG length, on all the others, use cache line length.